FIG. 1 is a view schematically showing a source driver according to the related art. The source driver includes a digital input stage 12, a digital to analog converter (DAC) 14, and an analog buffer stage 16. The source driver shown in FIG. 1 supplies a driving voltage for driving a data line to a panel, for example an LCD flat panel. Similarly, a gate driver applies a driving voltage for driving a gate line of a panel.
FIG. 2 is a graph illustrating characteristics of the buffer stage 16 in the source driver. The horizontal axis indicates the number of an individual output buffer and the vertical axis indicates an output voltage from each buffer. DVO indicates a deviation of the output voltage.
The digital input stage 12 receives digital data and outputs the data to the digital to analog converter 14. The DAC 14 converts the digital data into analog voltages, and the buffer stage 16 receives the converted analog voltages from the DAC 14, and outputs the driving voltage for driving the panel. The source driver may be integrated into a chip 10. The buffer stage 16 may be arranged with several hundred buffers 20, equal to the number of outputs of the source driver 10. The image quality of the panel depends on the characteristics of the source driver. The characteristics of the source driver depend on how equally the several hundred buffers generate outputs. However, when the same voltage is applied to the source driver, the outputs from the several hundred buffers may have a difference of tens to several hundred mV as shown in FIG. 2. This is caused by an offset generated in the fabricating process of the buffer. Therefore, to increase the yield of the chip 10, the offset characteristics should be good. Also, the improvement of the offset characteristics is intimately associated with the area of the chip. Therefore, a good offset and an optimal area are directly associated with the unit cost of the chip 10. Related methods for improving the output characteristic of the source driver have attempted only empirical approaches. Therefore, many revisions of repetitive chip designs have been demanded due to the empirical approaches, thereby increasing the development time and cost of the chip.